Add vsx register support for ppc inline asm, and implement preserves_flag option #146949

pmur · 2025-09-23T22:27:51Z

This should address the last(?) missing pieces of inline asm for ppc:

Explicit VSX register support. ISA 2.06 (POWER7) added a 64x128b register overlay extending the fpr's to 128b, and unifies them with the vmx (altivec) registers. Implementations details within gcc/llvm percolate up, and require using the x template modifier. I have updated the inline asm to implicitly include this for vsx arguments which do not specify it. ~~Support for the gcc codegen backend is still a todo.~~
Implement the preserves_flags option. All ABI's, and all ISAs store their flags in cr, and the carry bit lives inside xer. The other status registers hold sticky bits or control bits which do not affect branch instructions.

There is some interest in the e500 (powerpcspe) port. Architecturally, it has a very different FP ISA, and includes a simd extension called SPR (which is not IBM's cell SPE). Notably, it does not have altivec/fpr/vsx registers. It also has an SPE accumulator register which its ABI marks as volatile, but I am not sure if the compiler uses it.

rustbot · 2025-09-23T22:27:56Z

r? @jackh726

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pmur · 2025-09-23T22:29:24Z

r? @Amanieu
cc @taiki-e

rustbot · 2025-09-24T16:41:23Z

Some changes occurred in compiler/rustc_codegen_gcc

cc @antoyo, @GuillaumeGomez

pmur · 2025-09-24T16:43:15Z

For the gcc backend, what is the preferred way to test these changes?

antoyo · 2025-09-24T16:49:49Z

For now, we don't have gcc assembly or codegen tests, so I would leave this as is.

pmur · 2025-09-30T19:05:36Z

Ping.

Amanieu · 2025-09-30T18:41:57Z

compiler/rustc_codegen_gcc/src/asm.rs

-            extended_asm.add_clobber("cc");
+            match asm_arch {
+                InlineAsmArch::PowerPC | InlineAsmArch::PowerPC64 => {
+                    let clobbers = ["cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", "xer"];


It's not clear whether this is the approach we want to go with for PPC assembly. Currently we have the ability to explicitly mark cr* and xer as clobbers with out("cr0") _. Is this something that we want to preserve? Do we want these to always be marked as clobbered by default?

The choice here is very conservative. I think ISA is fairly explicit about which instructions clobber crs and/or xer. It's mostly cr0 (gpr . ops), cr6 (vsx/vmx . ops), and xer (the something and carry ops, and some shift ops).

For ergonomics, limiting this to cr0 and xer would capture the most common cases. Likewise if preserve_flags is not used when it should, it's not clobbering callee-save crs.

limiting this to cr0 and xer would capture the most common cases

Agreed. Most of cr* registers are not modified as a side effect of another instruction without explicitly specifying a register name. (Btw, in C/C++, "cc" is mapped to "cr0" (Clang, GCC).)

most of the FP ops clobber cr1 if you use the . variant.

Amanieu · 2025-10-03T23:37:52Z

src/doc/unstable-book/src/language-features/asm-experimental-arch.md

 | PowerPC      | `reg_nonzero`  | `r[3-12]`, `r[14-28]`              | `b`                  |
 | PowerPC      | `freg`         | `f[0-31]`                          | `f`                  |
 | PowerPC      | `vreg`         | `v[0-31]`                          | `v`                  |
+| PowerPC      | `vsreg         | `vs[0-63]`                         | `vs`                 |


Suggested change

| PowerPC | `vsreg | `vs[0-63]` | `vs` |

| PowerPC | `vsreg | `vs[0-63]` | `wa` |

rustbot · 2025-10-07T15:31:44Z

Some changes occurred in src/doc/unstable-book/src/compiler-flags/branch-protection.md

cc @rust-lang/project-exploit-mitigations, @rcvalle

cuviper · 2025-10-07T16:23:37Z

It seems your rebase dragged a few other commits with it...

rustbot · 2025-10-07T16:36:32Z

This PR was rebased onto a different master commit. Here's a range-diff highlighting what actually changed.

Rebasing is a normal part of keeping PRs up to date, so no action is needed—this note is just to help reviewers.

taiki-e · 2025-10-08T01:12:48Z

cc @programmerjake

programmerjake · 2025-10-08T02:16:38Z

compiler/rustc_codegen_gcc/src/asm.rs

-            extended_asm.add_clobber("cc");
+            match asm_arch {
+                InlineAsmArch::PowerPC | InlineAsmArch::PowerPC64 => {
+                    let clobbers = ["cr0", "xer"];


this should probably include cr1 for the FP . instructions and cr6 for the vector instructions. The rest of the cr fields should need explicit instruction arguments so are much less likely to be forgotten.

Using a dotted fp or vector op is almost always by explicit choice. I think in all cases, a non-dotted form available. The dotted fp usage is only useful when checking for fp exceptions.

xer and cr0 are used in common instructions with only dotted forms available, or always clobber xer[ca], subfic andi. srad come to mind.

programmerjake · 2025-10-08T02:25:25Z

compiler/rustc_target/src/asm/powerpc.rs

            },
+            // VSX is a superset of altivec.
+            Self::vsreg => types! {
+                vsx: F32, F64, VecI8(16), VecI16(8), VecI32(4), VecI64(2), VecF32(4), VecF64(2);


technically this should also include 128-bit integer/fp types and f16 since there are instructions for operating on those, but we can leave those out for now.

programmerjake · 2025-10-08T02:32:16Z

compiler/rustc_target/src/asm/powerpc.rs

+            vs63 : v31;
        }
-        // f0-f31 (vsr0-vsr31) and v0-v31 (vsr32-vsr63) do not conflict.
+        // For more detail, see ISA 3.1, Book I, Section 7.2.


Suggested change

// For more detail, see ISA 3.1, Book I, Section 7.2.

// For more detail, see Power ISA v3.1C, Book I, Section 7.2.1.1 and 7.2.1.2 on page 486 (522):

// https://files.openpower.foundation/s/9izgC5Rogi5Ywmm

Where supported, VSX is a 64x128b register set which encompasses both the floating point and vector registers. In the type tests, xvsqrtdp is used as it is the only two-argument vsx opcode supported by all targets on llvm. If you need to copy a vsx register, the preferred way is "xxlor xt, xa, xa".

Amanieu · 2025-10-09T17:22:11Z

I'm inclined to only have this cover cr0 for consistency with cc in GCC/Clang. Inline assembly users will already be used to marking xer and other cr* registers as explicit clobbers.

Also we may want to disallow specifying cr0 as an explicit clobber and have the error message point to preserves_flags instead. I would very much prefer not having 2 ways of doing the same thing.

pmur · 2025-10-09T19:10:02Z

Also we may want to disallow specifying cr0 as an explicit clobber and have the error message point to preserves_flags instead. I would very much prefer not having 2 ways of doing the same thing.

I think we want to allow both. As far as I can tell, the cc == cr0 behavior isn't documented, I wasn't aware it did anything on ppc until pointed out earlier.

As for xer, I think it should be included with the flags, but consistency with other toolchains is more important. I'll drop it.

Implemented preserves_flags similar to the `cc` pseudo-register on gcc and clang. The gcc inline documentation doesn't actually state what this does on powerpc* targets, but inspection of the source shows it is equivalent to condition register field `cr0`.

rustbot assigned jackh726 Sep 23, 2025

rustbot assigned Amanieu and unassigned jackh726 Sep 23, 2025

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pmur force-pushed the murp/improve-ppc-inline-asm branch from a258f60 to b63ecb2 Compare September 24, 2025 16:41

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Amanieu reviewed Oct 3, 2025

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pmur force-pushed the murp/improve-ppc-inline-asm branch from b63ecb2 to 57b0d79 Compare October 7, 2025 15:31

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pmur force-pushed the murp/improve-ppc-inline-asm branch from 57b0d79 to 47d8404 Compare October 7, 2025 16:36

programmerjake reviewed Oct 8, 2025

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pmur force-pushed the murp/improve-ppc-inline-asm branch from 47d8404 to 9d51dd0 Compare October 8, 2025 20:24

pmur force-pushed the murp/improve-ppc-inline-asm branch from 9d51dd0 to 05ad94b Compare October 9, 2025 20:51

	\| PowerPC \| `vsreg \| `vs[0-63]` \| `vs` \|
	\| PowerPC \| `vsreg \| `vs[0-63]` \| `wa` \|

	// For more detail, see ISA 3.1, Book I, Section 7.2.
	// For more detail, see Power ISA v3.1C, Book I, Section 7.2.1.1 and 7.2.1.2 on page 486 (522):
	// https://files.openpower.foundation/s/9izgC5Rogi5Ywmm

Add vsx register support for ppc inline asm, and implement preserves_flag option #146949

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Add vsx register support for ppc inline asm, and implement preserves_flag option #146949

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